Biography
I'm a Ph.D. student in Computer Science and Engineering at Politecnico di Milano, working at the Novel Emerging Computing System Technologies Laboratory (NECSTLab) under the guidance of professor Marco Santambrogio. My research is centered around high-performance computing for sparse linear algebra and graph analytics, with a focus on scalable FPGA and GPU computation, and making heterogeneous computing more accessible to everyone.
I've also been collaborating with Oracle Labs during my master thesis and Ph.D. and created really cool stuff together with the Pgx and GraalVM teams.
At NECSTLab, I'm currently leading the research and development of the GrCUDA project, in collaborations with Oracle Labs.
I've received my Bachelor's and Master's degrees at Politecnico di Milano and studied at the Ecole Polytechnique de Bruxelles.
I like things that go fast, making things go faster, macro photography, and hot enamel handicraft.
Selected Publications
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Parravicini, A., Cellamare, L. G., Siracusa, M., & Santambrogio, M. D. (2021, Dec).
Scaling up HBM Efficiency of Top-K SpMV for Approximate Embedding Similarity on FPGAs.
To appear in Proceedings of the 58th Design Automation Conference (DAC) (p. 6). Paper, Code -
Sgherzi, F., Parravicini, A., Siracusa, M., & Santambrogio, M. D. (2021, May).
Solving Large Top-K Graph Eigenproblems with a Memory and Compute-optimized FPGA Design.
In 2021 IEEE 29th Annual International Symposium on Field-Programmable Custom Computing Machines (FCCM) (p. 12). Paper -
Parravicini, A., Delamare, A., Arnaboldi, M., & Santambrogio, M. D. (2021, May).
DAG-based Scheduling with Resource Sharing for Multi-task Applications in a Polyglot GPU Runtime.
In 35th IEEE International Parallel & Distributed Processing Symposium (IPDPS) (p. 10). Paper, Code
Talks & Blogs
- DAG-based Scheduling for Multi-task Applications in a Polyglot GPU Runtime Presented at IPDPS 2021. Slides, Video
- A reduced-precision streaming SpMV architecture for Personalized PageRank on FPGA Presented at ASP-DAC 2021. Slides
- High-Performance Graph Queries (and friends) Lecture for the course High-Performance Data & Graph Analytics, Politecnico di Milano, 2020. Slides
- Fast Entity Linking via Graph Embeddings. Presented at GRADES-NDA 2019, Amsterdam. Slides
- Blog post on Entity Linking (a.k.a. Named Entity Disambiguation) on the Oracle Artificial Intelligence Blog. Part 1, Part 2
All Publications
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Parravicini, A., Cellamare, L. G., Siracusa, M., & Santambrogio, M. D. (2021, December).
Scaling up HBM Efficiency of Top-K SpMV for Approximate Embedding Similarity on FPGAs.
To appear in Proceedings of the 58th Design Automation Conference (DAC) (p. 6). Paper, Code -
Parravicini, A., Mueller, R. (2021, November).
The Cost of Speculation: Revisiting Overheads in the V8 JavaScript Engine.
To appear in Proceedings of the 2021 IEEE International Symposium on Workload Characterization (IISWC) (p. 11). -
Ramalli, E., Parravicini, A., Di Donato, G. W., Salaris, M., Hudelot, C., & Santambrogio, M. D. (2021, September).
Demystifying Drug Repurposing Domain Comprehension with Knowledge Graph Embedding.
In 2021 Biomedical Circuits and Systems Conference (BioCAS) (p. 5). Paper -
Di Donato, G.W., Damiani, A., Parravicini, A., Bionda, E., Soldan, F., Tornelli, C., & Santambrogio, M. D. (2021, September).
Towards Graph Machine Learning for Smart Grid Knowledge Graphs in Industrial Scenario.
In 2021 IEEE 6th International Forum on Research and Technology for Society and Industry (RTSI) (p. 4). -
Racchi, N., Di Donato, G. W., Parravicini, A., & Santambrogio, M. D. (2021, September).
Fraud Prevention and Detection on Heterogeneous Information Networks With Deep Graph Infomax.
In 2021 IEEE 6th International Forum on Research and Technology for Society and Industry (RTSI) (p. 4). -
Sgherzi, F., Parravicini, A., Siracusa, M., & Santambrogio, M. D. (2021, May).
Solving Large Top-K Graph Eigenproblems with a Memory and Compute-optimized FPGA Design.
In 2021 IEEE 29th Annual International Symposium on Field-Programmable Custom Computing Machines (FCCM) (p. 12). Paper -
Parravicini, A., Delamare, A., Arnaboldi, M., & Santambrogio, M. D. (2021, May).
DAG-based Scheduling with Resource Sharing for Multi-task Applications in a Polyglot GPU Runtime.
In 35th IEEE International Parallel & Distributed Processing Symposium (IPDPS) (p. 10). Paper, Code -
Parravicini, A., Sgherzi, F., & Santambrogio, M. D. (2021, January).
A reduced-precision streaming SpMV architecture for Personalized PageRank on FPGA.
In Proceedings of the 26th Asia and South Pacific Design Automation Conference (ASP-DAC) (p. 6). Paper -
Piccinotti, D., Ramalli, E., Parravicini, A., Brondolin, R., & Santambrogio, M. D. (2019, September).
Solving write conflicts in GPU-accelerated graph computation: a PageRank case-study.
In IEEE International Forum on Research and Technologies for Society and Industry (RTSI). IEEE. Paper -
Bertoldi, M. A., Cellamare, L., Parravicini, A., & Santambrogio, M. D. (2019, September).
Exploring transductive and inductive methods for vertex embedding in biological networks.
In IEEE International Forum on Research and Technologies for Society and Industry (RTSI). IEEE. Paper -
Parravicini, A., Patra, R., Bartolini, D. B., & Santambrogio, M. D. (2019, June).
Fast and Accurate Entity Linking via Graph Embedding.
In Proceedings of the 2nd Joint International Workshop on Graph Data Management Experiences & Systems (GRADES) and Network Data Analytics (NDA) (p. 10). ACM. Paper -
Stornaiuolo, L., Parravicini, A., Sciuto, D., & Santambrogio, M. D. (2018, May).
FIDA: a framework to automatically integrate FPGA kernels within Data-Science applications.
In 2018 IEEE International Parallel and Distributed Processing Symposium Workshops (IPDPSW) (pp. 198-201). IEEE. Paper -
Stornaiuolo, L., Parravicini, A., Durelli, G., & Santambrogio, M. D. (2017, May).
Exploiting fpgas from higher level languages a signal analysis case study.
In 2017 IEEE International Parallel and Distributed Processing Symposium Workshops (IPDPSW) (pp. 132-140). IEEE. Paper